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Past Exam for EEC 210 - MOS Analog Circuit Desgn with Amirtharajah at UC Davis (UCD)

Exam Information

Material Type:Mid-Term
Professor:Amirtharajah
Class:EEC 210 - MOS Analog Circuit Desgn
Subject:Engineering Electrical & Compu
University:University of California - Davis
Term:Fall 2008
Keywords:
  • Assumptions
  • Input Voltage
  • Transistors
  • Following Circuit
  • Output Voltage
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Sample Document Text

Name: EEC 210 Fall 2008 Midterm Rajeevan Amirtharajah Dept. of Electrical and Computer Engineering University of California, Davis November 13 , 2008 Instructions: This test consists of 4 problems and 14 pages, including the cover sheet. Please make sure that you have all of them. This is an open-book, open-notes test. State any assumptions you make and show complete work to receive credit. The time limit is 80 minutes. The problems are weighted as shown below: Grading: Sol\A.~ io'flS Problem Maximum Score 1 13 2 13 3 12 4 12 Total 50 1 V DD =5V Figure 1: Resistive load amplifier. 1 Resistive Load Amplifier Figure 1 shows a resistively loaded amplifier. Source Vss is a small-signal source only. For this problem, use the transistor parameters in Table 1. Parameter NMOS 'lit 1Y Ld 0 Xd 0 k' 300 p,A/y 2 "( 0 W / L 16/ 3 A 1/100 y-l Table 1: Problem 1 Transistor Parameters. Problem 1.1 (4 points) Find the large-signal input voltage VI such that ...

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