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Past Exam for EEC 210 - MOS Analog Circuit Desgn with Amirtharajah at UC Davis (UCD)

Exam Information

Material Type:Mid-Term
Professor:Amirtharajah
Class:EEC 210 - MOS Analog Circuit Desgn
Subject:Engineering Electrical & Compu
University:University of California - Davis
Term:Fall 2005
Keywords:
  • Assumptions
  • Following Circuit
  • Largest Value
  • Output Voltage
  • Engineering
  • Output Resistance
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EEC 210 Fall 2005 Midterm Rajeevan Amirtharajah Dept. of Electrical and Computer Engineering University of California, Davis November 15, 2005 Name: Instructions: This test consists of 4 problems and 13 pages, including the cover sheet. Please make sure that you have all of them. This is an open-book, open-notes test. State any assumptions you make and show complete work to receive credit. The time limit is 80 minutes. The problems are weighted as shown below Grading: Problem Maximum Score 1 12 2 16 3 10 4 12 Total 50 1 1 CMOS Inverter Amplifier Figure 1 shows a CMOS inverter biased as a linear amplifier. For this problem, use the transistor parameters in Table 1. Parameter NMOS PMOS Vt 1 V -1 V Ld 0 0 Xd 0 0 k' 300 ľA/V2 100 ľA/V2 ? 0 0 W/L 2 6 ? 0.1 V?1 0.1 V?1 Table 1: Problem 1 Transistor Parameters. Problem 1.1 (3 points) Assume VI = 1.5 V. For what range of VO will the circuit best act as an amplifier? What is the output voltage swing? Problem 1.2 (2 points) Find the powe...
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