Past Exam for EEC 210 - MOS Analog Circuit Desgn with Amirtharajah at UC Davis (UCD)

Exam Information

Material Type:Mid-Term
Class:EEC 210 - MOS Analog Circuit Desgn
Subject:Engineering Electrical & Compu
University:University of California - Davis
Term:Fall 2008
  • Assumptions
  • Input Voltage
  • Temperature
  • Following Circuit
  • Transistors
  • Output Voltage
  • Engineering
  • Output Resistance
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Sample Document Text

EEC 210 Fall 2008 Midterm Rajeevan Amirtharajah Dept. of Electrical and Computer Engineering University of California, Davis November 13, 2008 Name: Instructions: This test consists of 4 problems and 14 pages, including the cover sheet. Please make sure that you have all of them. This is an open-book, open-notes test. State any assumptions you make and show complete work to receive credit. The time limit is 80 minutes. The problems are weighted as shown below: Grading: Problem Maximum Score 1 13 2 13 3 12 4 12 Total 50 1 Figure 1: Resistive load ampli er. 1 Resistive Load Ampli er Figure 1 shows a resistively loaded ampli er. Source vss is a small-signal source only. For this problem, use the transistor parameters in Table 1. Parameter NMOS Vt 1 V Ld 0 Xd 0 k0 300 A/V2 0 W=L 16/3 1/100 V 1 Table 1: Problem 1 Transistor Parameters. Problem 1.1 (4 points) Find the large-signal input voltage VI such that the large-signal output voltage VO = 3V. You may ignore channel length mod...

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